This invention concerns a method to manufacture an electronic component, including a silicon wafer, usable in particular in smart cards. More particularly, the method aims to protect said component against the attacks designed to determine some of its operating characteristics and obtain some of its secret data, for fraudulent purposes. The invention also concerns such a component so realised.
Silicon wafer components have a front side and a back side. The front side has electronic components usually consisting of CMOS type transistors (N transistor and P transistor), comprising body ties or wells of N+ or P+ doped materials, to polarise the P-substrate and the N-moats for transistors with the same doping as the substrate. The thickness of a silicon wafer is usually about 600 to 700 microns, the maximum thickness of the active parts and the moats being about 10 microns.
We know that smart cards contain sensitive information and/or are used as means of communication to access such information. These cards are subject to fraudulent operations known as attacks, by persons trying to obtain this information illegally.
The traditional attacks are currently made from the front side (side supporting the active components). These attacks consist in injecting faults, by light radiation or other, or in sampling information by capture of electromagnetic radiation or other. These faults cause abnormal electronic behaviour of the integrated circuit, such as losses of information in the memories, incorrect memory reads, degradation of logic levels which can be incorrectly interpreted by the logic layers.
Currently therefore, the most frequent and efficient attacks occur on the front side, in a known manner.
The attackers, however, are starting to take an interest in the back side. This side is in fact easier to read (fewer disturbing elements such as the various metallisation layers connecting the transistors together). However, the thick silicon forms an absorbing barrier.
To cross the barrier, the attacks from the back side, in a known manner, consist in significantly thinning the silicon wafer (down to several tens of microns).
Currently, observation and/or disturbance of the component by the back side remains difficult due to the absorption by the silicon, but the thinning methods are making extremely rapid progress and it is clear that this type of attack is likely to become more and more important and the resulting threats will become extremely serious.
In addition, the manufacturers of such circuits need to know their operation, in order to test and/or debug them. These debugging methods lead to progress in the behaviour observation techniques seen from the back side, indirectly contributing to the development of new techniques for the attackers.
The investigation operations, whether as malicious attacks or for testing or debugging purposes, include a step to thin the silicon wafer down to a thickness of less than about 200 microns, or even several tens of microns.
This thinning does not disturb the operation of the circuit or of its components (transistors).
We also know that the silicon substrate must be very highly polarised to avoid destruction (e.g. latch up or malfunctions caused by modified electrical characteristics of the transistors).
Consequently, in a known manner, polarisation connections are planned on the front side of the silicon wafer, as body ties of doped material, to offer a constant level of potential for the substrate and the polarisation moats of the P transistors. Each polarisation connection provides equipotentiality over a radius of about 50 microns, so one polarisation connection can be associated with a group of about 5 to 20 transistors.
For the N transistors, the polarisation connection consists of a P+ doped connection, connected to the potential VSS, of width about 1 micron and depth a few microns. For the P transistors, the polarisation connection consists of a body tie as an N+ doped well polarising the N-moat, which includes the P+ doped body ties forming the transistor. Said body tie forming a polarisation connection is connected to the potential VDD (5 or 3 volts).